TSMC shares more information on 2nm: details on the new MIM capacitor and PDN back

TSMC shares more information on 2nm: details on the new MIM capacitor and PDN back

TSMC revealed some additional details about its upcoming N2 and N2P process technology at its European Technology Symposium 2023. Both manufacturing nodes were developed with high-performance computing (HPC) in mind, so they feature a number of enhancements designed specifically for improve performance. Meanwhile, given the focus on performance efficiency that most chips aim to improve upon, even low-power applications will benefit from TSMC’s N2 nodes as they will naturally improve performance per watt over their predecessors.

“N2 is a perfect fit for the energy-efficient computing paradigm we’re in today,” said Yujun Li, director of business development at TSMC, in charge of the foundry’s high-performance computing business division, at the European Technology Symposium 2023 in Dell. ‘agency. The speed and power advantages of N2 over N3 over the entire voltage supply range, as shown, are very consistent, making it suitable for both low-power and high-performance applications at the same time.”

TSMC’s N2 Production Node – the first production nodes in the foundry to use nanosheet gate-all-around (GAAFET) transistors – promises to increase transistor performance by 10-15% for the same power and complexity, or reduce the 25-30% power consumption at the same clock speed and transistor count. Power delivery is one of the cornerstones when it comes to enhancing transistor performance, and TSMC’s N2 and N2P manufacturing processes introduce several innovations related to interconnects to achieve additional performance. Additionally, N2P introduces the power rail on the rear to optimize power delivery and die area.

Fighting resistance

One of the innovations that N2 brings to the table is the ultra-high performance metal-insulator-to-metal capacitor (SHPMIM) to improve power supply stability and facilitate on-chip decoupling. TSMC says the new SHPMIM capacitor offers more than 2x the capacitance density of its ultra-high-density metal-insulator-to-metal capacitor (SHDMIM) introduced several years ago for HPC (which increased the capacitance by 4x over the previous generation HDMIM) . The new SHPMIM also reduces Rs (Ohm/Square) sheet resistance by 50% compared to SHDMIM and Rc via resistance by 50% compared to SHDMIM.

Yet another way to reduce resistance in the supply network was to redesign the redistribution level (RDL). Starting with its N2 process technology, TSMC will use a copper RDL instead of today’s aluminum RDL. A copper RDL will give a similar RDL step, but will reduce sheet resistance by 30% and reduce resistance by 60%.

Both SHPMIM and Cu RDL are part of TSMC’s N2 technology which is expected to be used for high volume manufacturing (HVM) in the second half of 2025 (presumably very late in 2025).

Decoupling of power and I/O wiring

The use of a Power Distribution Network (PDN) at the rear is another major improvement that will feature N2P. The general advantages of the rear power rail are well known: by separating I/O and power cables by moving the power rails to the rear, it is possible to make the power cables thicker and thus reduce them via the resistors in the back-end-of-line ( BEOL), which promises to improve performance and reduce power consumption. Also, decoupling the I/O and power cables allows you to reduce the logic area, which means lower costs.

At its Technology Symposium 2023, the company revealed that its N2P’s rear PDN will enable 10% to 12% higher performance by reducing IR dropout and improving signaling, as well as reducing the logical area by 10% to 15%. Now, of course, those benefits will be most apparent in high-performance CPUs and GPUs that have a tight power grid and so moving it to the rear makes a lot of sense to them.

Backside PDN is part of TSMC’s N2P fabrication technology that will enter HVM in late 2026 or early 2027.

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